Semiconductor memories generally include a multitude of memory cells arranged in rows and columns. Each memory cell is capable of storing digital information in the form of a "1" or a "0" bit. To write (i.e., store) a bit into a memory cell, a binary memory address having portions identifying the cell's row (the "row address") and column (the "column address") is provided to addressing circuitry in the semiconductor memory to activate the cell, and the bit is then supplied to the cell. Similarly, to read (i.e., retrieve) a bit from a memory cell, the cell is again activated using the cell's memory address, and the bit is then output from the cell.
Semiconductor memories are typically tested after they are fabricated to determine if they contain any failing memory cells (i.e., cells to which bits cannot be dependably written or from which bits cannot be dependably read). Generally, when a semiconductor memory is found to contain failing memory cells, an attempt is made to repair the memory by replacing the failing memory cells with redundant memory cells provided in redundant rows or columns in the memory.
Conventionally, when a redundant row is used to repair a semiconductor memory containing a failing memory cell, the failing cell's row address is permanently stored (typically in pre-decoded form) on a chip on which the semiconductor memory is fabricated by programming a non-volatile element (e.g., a group of fuses, anti-fuses, or FLASH memory cells) on the chip. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a row address that corresponds to the row address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant row to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell's row has the same row address, every cell in the failing cell's row, both operative and failing, is replaced by a redundant memory cell in the redundant row.
Similarly, when a redundant column is used to repair the semiconductor memory, the failing cell's column address is permanently stored (typically in pre-decoded form) on the chip by programming a non-volatile element on the chip. Then, during normal operation of the semiconductor memory, if the memory's addressing circuitry receives a memory address including a column address that corresponds to the column address stored on the chip, redundant circuitry in the memory causes a redundant memory cell in the redundant column to be accessed instead of the memory cell identified by the received memory address. Since every memory cell in the failing cell's column has the same column address, every cell in the failing cell's column, both operative and failing, is replaced by a redundant memory cell in the redundant column.
From the discussion of semiconductor memories thus far, it may appear that such memories comprise one large array of memory cells. This is true as far as other electronic devices are concerned, because such devices typically interact with a semiconductor memory as if it were a single array of memory cells arranged in as many rows and columns (referred to as "global" rows and columns) as are uniquely addressable by the memory's row and column addresses.
For the reliability improvement, it is necessary to identify whether the burn-in fail devices and the customer return devices are repaired devices or not. However, after assembly, the break of the laser fuse cannot be observed visually. Therefore, it is required that the repaired memory device can be identified electrically. A laser signature circuit is normally used for this purpose.
A laser signature circuit in a memory device comprises a fuse. When the fuse in a failing cell is broken by using laser technology, the fuse in the laser signature circuit of the failing device is broken at the same time. Accordingly, the status of the memory device is determined by using the fuse in the laser signature circuit.
Referring to FIG. 1, it is mentioned that a memory circuit comprises a laser signature circuit in accordance with prior art, electrostatic-discharge (ESD) protective devices are connected to an input pin and an internal circuit of the memory circuit.
Still referring to FIG. 1, a signal is input from an input pin 100 of a memory device for accessing or storing data into an internal circuit 200. The input pin 100 is connected to the internal circuit 200. Additionally, several electrostatic-discharge (ESD) devices 130 and several clamping devices 130 are connected to the input pin 100 and the internal circuit 200. The ESD device 130 consists of thick gate n-channel metal-oxide-semiconductor (MOS) transistors (field oxide devices) for limiting the electrostatic-discharge (ESD) pulse inputting from the input pin 100. The laser signature circuit consists of a fuse 110 and several diodes 120. In detail, a terminal of the laser signature circuit is connected to the input pin 100 and the internal circuit 200, the other terminal of the laser signature circuit is the power pin V.sub.DD. The V.sub.T (threshold voltage) of the thick gate MOS transistor 130 is normally much higher than twice of the V.sub.T of the thin gate MOS transistor in the laser signature circuit 120.
When the memory cells of the internal circuit 200 are repaired by laser technology, the fuse 110 is melted (i.e. opened) by using laser light. As operator wants to identify whether the memory cells of the internal circuit 200 are repaired, the fuse 110 is tested by applying a voltage on the input pin 100. The applied voltage is higher than V.sub.DD (power supply voltage) plus twice of the threshold voltage of the thin gate MOS transistor, and is lower than V.sub.DD plus threshold voltage of the thick gate MOS transistor. The current on the input pin 100 is then measured. If the fuse 110 has not been broken by the laser, the current on the input pin 100 can be detected and that means that the memory devices in the internal circuit 200 are not repaired.
Nevertheless, as the shallow-trench-isolation (STI) technique is adapted to fabricate the isolation regions between the active regions in deep submicron semiconductor devices the conducting of the thick gate n-channel MOS transistor (a field oxide device) occurs at a voltage (at input pin 100) higher than the breakdown voltage of the gate oxide of the thin gate oxide MOS transistors in the internal circuit 200. Consequently, the ESD devices 130 must consist of thin gate MOS transistors. The use of thin gate oxide device as ESD device 130 also serve as clamping device to reduce the overshot and undershot noise at the input pin 100. However, in this case the laser signature circuit no longer work, because device 130 becomes conducting at lower input voltage (at input pin 100) than that of the device 120 in the laser signature circuit.
It is needed that a laser signature circuit is connected to input pins of a memory device for identifying the status of the memory cells in the memory device and it is useful when thin gate ESD devices are connected to the input pins for limiting the electrostatic-discharge pulse occurred on the input pins.